21150 - DFT (ATPG) Engineer

Qualitest is the world’s leading AI-powered Quality Engineering company. 
With 8,000+ experts worldwide and 1,500 in Israel, we partner with top global brands to deliver smarter, faster, and more reliable technology solutions. 
For the fifth year in a row, Qualitest has been recognized as one of Israel’s Top 100 Best Places to Work, reflecting our commitment to a stable, supportive, and growth-oriented workplace. 

Your next career move starts here: Team Leader QA Tester – Israel  

Responsibilities:

• Develop DFT strategy for hierarchical DFT, Scan, and Automatic Test Pattern Generation (ATPG MUST HAVE)
• Perform ATPG, scan coverage debug and drive design fixes for coverage and quality improvements
• Perform scan verification at RTL and gate level
• Prepare scan content and delivarables for Silicon Engineering execution
• Debug scan patterns on tester per requirement
• Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT Scan requirements are met and mutual dependencies are managed.

Requirements:

•  Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
• Experience with multiple projects in DFT scan design and verification.
• Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.
• 4 years of experience in Automatic Test Pattern Generation (ATPG) methods.
• Familiar with EDA tools like mentor ( tessent) from Siemens - Advantage.
• Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and Memory Built-In Self Test (MBIST)). -  Advantage.
• Experience in fault modeling. -  Advantage. 
• Experience in SoC cycles, including silicon bringup and silicon debug activities. -  Advantage.
• Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, debug of silicon issues). -  Advantage.