Formal Verification Engineer

Formal Verification (Property Checking) Engineer

• We are seeking a highly skilled Formal Verification Engineer to join Google HPC project.
• In this role, you will be responsible for applying property checking, model checking, and assertion-based verification techniques to ensure the functional correctness and complitness of Chiplet design that contain multi processors and Highspeed I/Os.
• You will collaborate closely with RTL designers, Contribute to the DV team verification efforts in achieving coverage clouse.

Key Responsibilities

• Formal Verification & Property CheckingDevelop, implement, and optimize SystemVerilog Assertions (SVA) and Properties.
• Perform end-to-end formal property checking for RTL blocks, subsystems, and full-chip components.
• Analyze design intent and create abstract models, constraints, and assumptions required for bounded or unbounded proofs.
• Identify Bugs, unreachable coverage points, dead code, vacuous proofs.
• All in effort to achieve 100% Verification coverage.
• Debug counterexamples, failures, and proof complexities using Jasper Gold, VCF & Questa Formal.

Collaboration & Methodology

• Work closely with VLSI design teams to understand specifications and derive formal properties.
• Partner with peers in DV to ensure consistency between formal and dynamic verification environments.
• Contribute to development and refinement of UVM, Coverage goals, etc.Tools & Infrastructure
• Use industry‑standard tools such as:Cadence JasperGold, Synopsys VC Formal, Siemens/Mentor Questa Formal, OneSpinDevelop scripts and utilities (Python, Perl, TCL, etc.) to automate flows, analyze coverage, and manage regressions.

Required Qualifications

• B.Sc./M.Sc. in Electrical Engineering, Computer Engineering, Computer Science, Mathematics, Physics.
• Strong knowledge of HDL in RTL (VHDL, SystemVerilog or Verilog), Digital design, High Level Modeling / TLM (SystemC, ARM TLM/CTL).
• Hands-on experience with formal verification methodologies including property checking, abstraction, assumptions/constraints modeling.Proficiency with SVA, PSL.Experience with at least one formal verification tool (Jasper Gold/VC Formal/Questa Formal).
• Strong debugging and problem‑solving skills, particularly analyzing proofs and counterexamples.

Preferred Qualifications

• Experience in working on Semiconductors HPC Device
• Experience verifying complex FSM, DSP, MCU, CPU, AXI subsystem, DDR, PCIe, HBM Familiarity with UVM, simulation-based verification flows.
• Knowledge of model checking theory, SAT/SMT solvers, or formal math‑based verification techniques.
• Strong scripting/programming experience (Python/TCL/Perl).

Soft Skills

• Excellent analytical thinking and attention to detail.
• Ability to communicate HDL/RTL modeling concepts clearly
• Self-driven, proactive, and comfortable working in a fast-paced engineering environment.
• Strong collaboration skills for cross-team engagement with architects, designers, and verification engineers.