DFT Engineer

Qualitest is the world’s leading AI-powered Quality Engineering company. 

With 8,000+ experts worldwide, we partner with top global brands to deliver smarter, faster, and more reliable technology solutions. 

Your next career move starts here: DFT Engineer

Responsibilities:

• Develop DFT strategy for hierarchical DFT, Scan, and Automatic Test Pattern Generation (ATPG).
• Perform scan coverage debug and drive design fixes for coverage and quality improvements
• Perform scan verification at RTL and gate level
• Prepare scan content and delivarables for Silicon Engineering execution
• Debug scan patterns on tester per requirement
• Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT Scan requirements are met and mutual dependencies are managed.

Requirements: 

• 4 years of experience in DFT 
• Mentor flow using Tessent tool
• Identify and fix DRC issues related to SCAN
• ATPG simulations for SCAN
• Experience in MBIST insertion and debug flow Synopsys or Mentor flow
• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
• Experience with multiple projects in DFT scan design and verification.
• Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.
• Familiar with EDA tools like mentor ( tessent) from Siemens. - Nice to have.
• Master's degree in Electrical Engineering. - Nice to have.
• Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and Memory Built-In Self Test (MBIST). - Nice to have. 
• Experience in fault modeling. - Nice to have. 
• Experience in SoC cycles, including silicon bringup and silicon debug activities. - Nice to have.