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CAD Design Verification Engineer

Date:  29 Aug 2024
Company:  Qualitest Group
Collaborate with ASIC teams to support CAD tools, solutions and methodologies for ASIC development. Experience with System verilog languageExperience in scripting languages (Unix Shell, Python) used to build tools and flows.Experience with ASIC design, debug, and verification flows.Experience with delivering chip design infrastructure and/or methodology including Multi-HDL model builds and CI/CD systems.

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