#22094-CoE - DE- DFT-ATPG Engineer

Date: 12 May 2026

Company: Qualitest Group

Country/Region: IN

Job responsibilities:Develop DFT strategy for hierarchical DFT, Scan, and Automatic Test Pattern Generation (ATPG).Perform ATPG, scan coverage debug and drive design fixes for coverage and quality improvementsPerform scan verification at RTL and gate levelPrepare scan content and delivarables for Silicon Engineering executionDebug scan patterns on tester per requirementWork with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT Scan requirements are met and mutual dependencies are managed.Minimum qualifications:Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.Experience with multiple projects in DFT scan design and verification.Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.4 years of experience in Automatic Test Pattern Generation (ATPG) methods.Preferred qualifications:Familiar with EDA tools like mentor ( tessent) from Siemens . Master's degree in Electrical Engineering.Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and Memory Built-In Self Test (MBIST)).Experience in fault modeling.Experience in SoC cycles, including silicon bringup and silicon debug activities.Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, debug of .silicon issues)